i-manager Publications

i-manager's Journal on Circuits and Systems (JCIR)

Current Issue Vol. 11 Issue 2

Voltage Stability and Power Loss Minimization with UPFC using Heuristic and Hybrid Heuristic Methods
Design and Analysis of Voltage Difference Transconductance Amplifier (VDTA) at FINFET CMOS Technology
Efficient Logic Cell Design for Ultralow-Energy Subthreshold Operation in Wearable Biomedical Systems
Design and Optimization of MSI-Enabled Multi-Precision Binary Multiplier Architecture
Analysis of Carbon Nanotube for Low Power Nano Electronics Applications

Most Cited

Volume 9 Issue 2 July - December 2021

Research Paper

Power and Ground Bounce Reduction Techniques for Nanoscale VLSI Systems

M. Kavitha*

Department of Electronics and Communication Engineering, Government College of Engineering, Bargur, Tamilnadu, India.

Kavitha, M. (2021). Power and Ground Bounce Reduction Techniques for Nanoscale VLSI Systems. i-manager's Journal on Circuits and Systems, 9(2), 1-8. https://doi.org/10.26634/jcir.9.2.18473

Abstract

In the field of nanotechnology, leakage noise and ground reflections have become important considerations in the design of VLSI circuits. Power leakage is a serious problem, especially in handheld and portable battery powered devices, due to critical battery life. Ground bounce can cause false transactions, resulting in incorrect values in digital circuits. In nanoscale VLSIs, the problem of reducing leakage and ground bounce needs to be addressed in order to improve circuit performance. In this paper, two power gating techniques to minimize leakage and ground bounce are proposed. Leakage power and ground bounce noise are estimated for ISCAS'85 benchmark circuits and simulation results reveal that the proposed techniques mitigate maximum of 79% leakage power and 60% ground bounce than conventional techniques.

References

[1]. Agarwal, K., Deogun, H., Sylvester, D., & Nowka, K. (2006, March). Power gating with multiple sleep modes. In 7^th International Symposium on Quality Electronic Design (ISQED'06) (pp. 5-pp). IEEE. https://doi.org/10.1109/ISQED. 2006.102

[2]. Hansen, M. C., Yalcin, H., & Hayes, J. P. (1999). Unveiling the ISCAS-85 benchmarks: A case study in reverse engineering. IEEE Design & Test of Computers, 16(3), 72-80. https://doi.org/10.1109/54.785838

[3]. Jiao, H. (2012). Noise mitigation in low leakage MTCMOS circuits (Doctoral dissertation). The Hong Kong University of Science and Technology, Hong Kong.

[4]. Khaled, P., Xu, J., & Chowdhury, M. H. (2007, August). Dual diode-Vth reduced power gating structure for better leakage reduction. In 2007, 50^th Midwest Symposium on Circuits and Systems (pp. 1409-1412). IEEE. https://doi.org/ 10.1109/MWSCAS.2007.4488810

[5]. Kim, S., Kosonocky, S. V., & Knebel, D. R. (2003, August). Understanding and minimizing ground bounce during mode transition of power gating structures. In Proceedings of the 2003 International Symposium on Low power Electronics and Design (pp. 22-25). https://doi.org/10.11 45/871506.871515

[6]. Kim, S., Kosonocky, S. V., Knebel, D. R., Stawiasz, K., & Papaefthymiou, M. C. (2007). A multi-mode power gating structure for low-voltage deep-submicron CMOS ICs. IEEE Transactions on Circuits and Systems II: Express Briefs, 54(7), 586-590. https://doi.org/10.1109/TCSII.2007.894428

[7]. Liu, Z., & Kursun, V. (2007, August). Low energy MTCMOS with sleep transistor charge recycling. In 2007, 50^th Midwest Symposium on Circuits and Systems (pp. 891-894). IEEE. https://doi.org/10.1109/MWSCAS.2007.4488714

[8]. Lorenzo, R., & Chaudhary, S. (2013, December). A novel all NMOS leakage feedback with data retention technique. In 2013, International Conference on Control, Automation, Robotics and Embedded Systems (CARE) (pp. 1-5). IEEE. https://doi.org/10.1109/CARE.2013.6733701

[9]. Mutoh, S. I., Douseki, T., Matsuya, Y., Aoki, T., Shigematsu, S., & Yamada, J. (1995). 1-V power supply high-speed digital circuit technology with multithresholdvoltage CMOS. IEEE Journal of Solid-state circuits, 30(8), 847-854. https://doi.org/10.1109/4.400426

[10]. Narendra, S., De, V., Antoniadis, D., Chandrakasan, A., & Borkar, S. (2001, August). Scaling of stack effect and its application for leakage reduction. In Proceedings of the 2001 International Symposium on Low Power Electronics and Design (pp. 195-200). https://doi.org/10.1145/3830 82.383132

[11]. Pakbaznia, E., & Pedram, M. (2011). Design of a trimodal multi-threshold CMOS switch with application to data retentive power gating. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 20(2), 380-385. https://doi.org/10.1109/TVLSI.2010.2102054

[12]. Roy, K., & Prasad, S. C. (2009). Low-power CMOS VLSI Circuit Design. John Wiley & Sons.

[13]. Tada, A., Notani, H., & Numa, M. (2006). A novel power gating scheme with charge recycling. IEICE Electronics Express, 3(12), 281-286. https://doi.org/10.15 87/elex.3.281

[14]. Taur, Y. (2002). CMOS design near the limit of scaling. IBM Journal of Research and Development, 46(2.3), 213- 222.

[15]. Xu, J. (2008). Perform the SPICE simulation of ISCAS85 benchmark circuits for research. Electrical and Computer Engineering, University of Illinois at Chicago.

[16]. Yang, S., Wolf, W., Vijaykrishnan, N., Xie, Y., & Wang, W. (2005, January). Accurate stacking effect macro modeling of leakage power in sub-100 nm circuits. In 18^th International Conference on VLSI Design held jointly with 4^th International Conference on Embedded Systems Design (pp. 165-170). IEEE. https://doi.org/10.1109/ICVD.2005.41

[17]. Zhao, W., & Cao, Y. (2006). New generation of predictive technology model for sub-45 nm early design exploration. IEEE Transactions on Electron Devices, 53(11), 2816-2823. https://doi.org/10.1109/TED.2006.884077

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Research Paper

Implementation of Seven-Level Reversing Voltage Inverter using Multi Reference Based Space Vector PWM Technique

S. Nagaraja Rao* , D. V. Ashok Kumar, CH. Sai Babu*

*-***Department of Electrical and Electronics Engineering, Jawaharlal Nehru Technological University, Kakinada, Andhra Pradesh, India.

Rao, S. N., Kumar, D. V. A., and Babu, C. H. S. (2021). Implementation of Seven-Level Reversing Voltage Inverter using Multi Reference Based Space Vector PWM Technique. i-manager's Journal on Circuits and Systems, 9(2), 9-15. https://doi.org/10.26634/jcir.9.2.15789

Abstract

In this paper, a cascade topology of a multilevel reverse voltage (RV) inverter has been proposed to improve multilevel performance by compensating for the shortcomings of two-level and conventional multilevel inverters (MLI). This topology requires less number of parts compared to existing MLI's particularly in higher levels with less gate drives and carrier signals. Therefore, the total cost and complication are greatly reduced, predominantly for higher output voltage levels. The suggested topology can have the improved performance by employing the most relevant control and modulation methods based on multiple space vector references with single U-type carrier wave. The paper persistently attempts to present the analysis carried out using space vector modified PWM control methods based on several references for the topology of a single-phase seven-level RV inverter in terms of total harmonic distortion (THD) and fundamental RMS voltage. Finally, simulation results are included to test the effectiveness of the proposed RV topology. A hardware setup has been developed to match the simulation results of a single-phase seven-level FPGA-based pulse-generated RV cascade inverter.

References

[1]. Cheng, Y., Qian, C., Crow, M. L., Pekarek, S., & Atcitty, S. (2006). A comparison of diode-clamped and cascaded multilevel converters for a STATCOM with energy storage. IEEE Transactions on Industrial Electronics, 53(5), 1512- 1521. https://doi.org/10.1109/TIE.2006.882022

[2]. Ebrahimi, J., Babaei, E., & Gharehpetian, G. B. (2011). A new topology of cascaded multilevel converters with reduced number of components for high-voltage applications. IEEE Transactions on Power Electronics, 26(11), 3109-3118. https://doi.org/10.1109/TPEL.2011.214 8177

[3]. Malinowski, M., Gopakumar, K., Rodriguez, J., & Perez, M. A. (2009). A survey on cascaded multilevel inverters. IEEE Transactions on Industrial Electronics, 57(7), 2197-2206. https://doi.org/10.1109/TIE.2009.2030767

[4]. Maruthupandi, P., Devarajan, N., Sebasthirani, K., & Jose, J. K. (2015). Optimum control of total harmonic distortion in field programmable gate array-based cascaded multilevel inverter. Journal of Vibration and Control, 21(10), 1999-2005. https://doi.org/10.1177/10775 46313504223

[5]. Najafi, E., & Yatim, A. H. M. (2011). Design and implementation of a new multilevel inverter topology. IEEE Transactions on Industrial Electronics, 59(11), 4148-4154. https://doi.org/10.1109/TIE.2011.2176691

[6]. Radan, A., Shahirinia, A. H., & Falahi, M. (2007, June). Evaluation of carrier-based PWM methods for multi-level inverters. In 2007, IEEE International Symposium on Industrial Electronics (ISIE 2007) (pp. 389-394). IEEE. https://doi. org/10.1109/ISIE.2007.4374629

[7]. Rao, S. N., Kumar, D. A., & Babu, C. S. (2013, February). New multilevel inverter topology with reduced number of switches using advanced modulation strategies. In 2013, International Conference on Power, Energy and Control (ICPEC) (pp. 693-699). IEEE. https://doi.org/10.1109/ICPEC. 2013.6527745

[8]. Rao, S. N., Kumar, D. A., & Babu, C. S. (2017). Multilevel inverter topology for distributed generation with high voltage gain cascaded DC-DC converter. Journal of Advanced Research in Dynamical and Control Systems (JARDCS), 9(1), 264-282.

[9]. Rodriguez, J., Lai, J. S., & Peng, F. Z. (2002). Multilevel inverters: A survey of topologies, controls, and applications. IEEE Transactions on Industrial Electronics, 49(4), 724-738. https://doi.org/10.1109/TIE.2002.801052

[10]. Su, G. J., & Adams, D. J. (2001, September). Multilevel DC link inverter for brushless permanent magnet motors with very low inductance. In Conference Record of the 2001 IEEE Industry Applications Conference. 36^th IAS Annual Meeting (cat. No. 01CH37248) (Vol. 2, pp. 829- 834). IEEE. https://doi.org/10.1109/IAS.2001.955549

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Research Paper

Implementation of Pipelined ADC using 22 nm FinFET Technology

M. Chandra Sekhar Reddy*

Department of Electronics and Communication Engineering, Sree Vidyanikethan Engineering College, Tirupati, Andhra Pradesh, India.

Reddy, M. C. S. (2021). Implementation of Pipelined ADC using 22 nm FinFET Technology. i-manager's Journal on Circuits and Systems, 9(2), 16-22. https://doi.org/10.26634/jcir.9.2.15094

Abstract

This paper presents a 4-stage pipelined analog to digital converter (ADC) architecture with a 4-bit resolution per each stage, enabled with the help of a successive approximation register (SAR) based sub-ADC. Successive approximation register (SAR) ADC architectures are popular for achieving high energy efficiency, low power applications but they suffer from resolution and speed limitations. To overcome the speed limitations of SAR ADC we propose the systematic design approach of a low-power, high-speed pipelined ADC. The power consumptions of the capacitive digital to analog converter (DAC), two stage FinFET comparator with output inverter of the proposed ADC are lower than those of a conventional ADC. ADC is designed in 22 nm FinFET technology with medium sampling rate and 16-bit resolution are achieved.

References

[1]. Abo, A. M., & Gray, P. R. (1999). A 1.5-V, 10-bit, 14.3-MS/s CMOS pipeline analog-to-digital converter. IEEE Journal of Solid-State Circuits, 34(5), 599-606. https://doi.org/10.110 9/4.760369

[2]. Baker, R. J. (2011). CMOS: Circuit Design, Layout, and Simulation. John Wiley & Sons.

[3]. Duarte, J. P., Paydavosi, N., Venugopalan, S., Sachid, A., & Hu, C. (2013, September). Unified FinFET compact model: modelling trapezoidal triple-gate FinFETs. In 2013, International Conference on Simulation of Semiconductor Processes and Devices (SISPAD) (pp. 135-138). IEEE. https:// doi.org/10.1109/SISPAD.2013.6650593

[4]. Oskuii, S. T. (2004). Comparative study on low-power high-performance flip-flops (Dissertation). Department of Electrical Engineering, Linköping University, Sweden.

[5]. Rahou, F. Z., Guen-Bouazza, A., & Rahou, M. (2013). Electrical characteristics comparison between fullydepleted SOI MOSFET and partially-depleted SOI MOSFET using Silvaco software. Global Journal of Research in Engineering, 13(1), 1-6.

[6]. Rai, A., & Venkatesan, B. A. (2014). Analysis and design of high speed low power comparator in ADC. International Journal of Engineering Development and Research (IJEDR), 2(1), 1015- 1020.

[7]. Reyes, B. T., Biolato, L., Galetto, A. C., Passetti, L., Solis, F., & Hueda, M. R. (2019). An energy-efficient hierarchical architecture for time-interleaved SAR ADC. IEEE Transactions on Circuits and Systems I: Regular Papers, 66(6), 2064-2076. https://doi.org/10.1109/TCSI.2019.2901 795

[8]. Rossi, A., & Fucili, G. (1996). Nonredundant successive approximation register for A/D converters. Electronics Letters, 32(12), 1055-1057.

[9]. Sowmya, T., Nihal, S. M., & Chand, D. G. (2018). Implementation of 16-bit pipelined ADC using 180 nm CMOS technology. International Research Journal of Engineering and Technology, 5(3), 591-595.

[10]. Tual, S. L., Singh, P. N., Curis, C., & Dautriche, P. (2014, February). 22.3 A 20GHz-BW 6b 10GS/s 32mW timeinterleaved SAR ADC with Master T&H in 28nm UTBB FDSOI technology. In 2014, IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC) (pp. 382- 383). IEEE. https://doi.org/10.1109/ISSCC.2014.6757479

[11]. Yee, Y. S., Terman, L. M., & Heller, L. G. (1979). A twostage weighted capacitor network for D/A-A/D conversion. IEEE Journal of Solid-State Circuits, 14(4), 778-781. https://doi.org/10.1109/JSSC.1979.1051264

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Research Paper

Design and Implementation of Low Power and High-speed Braun Multiplier using Hybrid Full Adder

I. Omesh* , B. Supriya, Carol Schubert, A. Likitha, D. Aditya

*-***** Department of Electronics and Communication Engineering, Lendi Institute of Engineering and Technology, Vizianagaram, Andhra Pradesh, India.

Omesh, I., Supriya, B., Yamini, Y., Likitha, A., and Aditya, D. (2021). Design and Implementation of Low Power and Highspeed Braun Multiplier using Hybrid Full Adder. i-manager's Journal on Circuits and Systems, 9(2), 23-29. https://doi.org/10.26634/jcir.9.2.16831

Abstract

This article proposes new schemes for XOR/XNOR and concurrent XOR-XNOR functions. Due to low output capacitance and low short-circuit power dissipation, these circuits are well optimized in terms of power consumption and delay. Six novel hybrid 1-bit full adder (FA) circuits based on full-swing XOR/XNOR gates are also available. In terms of speed, power consumption, power delay product (PDP), driving ability, etc., each of these circuits has unique benefits. Extensive Mentor Graphics is used to study the performance of the designs. The simulation findings, which are based on a 130 nm CMOS process technology model, show that the suggested designs outperform previous FA solutions in terms of speed and power. To improve the PDP of the circuits, a novel transistor size strategy is provided. The approach employs a numerical computing particle swarm optimization algorithm to reach the target PDP value with fewer repetitions. The circuits are examined in terms of supply and threshold voltage fluctuations, output capacitance, input noise immunity, and transistor size.

References

[1]. Bui, H. T., Wang, Y., & Jiang, Y. (2002). Design and analysis of low-power 10-transistor full adders using novel XOR-XNOR gates. IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, 49(1), 25-30. https://doi.org/10.1109/82.996055

[2]. Goel, S., Kumar, A., & Bayoumi, M. A. (2006). Design of robust, energy-efficient full adders for deepsubmicrometer design using hybrid-CMOS logic style. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 14(12), 1309-1321. https://doi.org/10.1109/TVLSI.2006.887 807

[3]. Kim, N. S., Austin, T., Baauw, D., Mudge, T., Flautner, K., Hu, J. S., ... & Narayanan, V. (2003). Leakage current: Moore's law meets static power. Computer, 36(12), 68-75. https://doi.org/10.1109/MC.2003.1250885

[4]. Paradhasaradhi, D., & Anusudha, K. (2013). An area efficient enhanced SQRT carry select adder. International Journal of Engineering Research and Applications, 3(6), 876-880.

[5]. Rabaey, J. M., Chandrakasan, A. P., & Nikolic, B. (2002). Digital Integrated Circuits (Vol. 2). Englewood Cliffs: Prentice hall.

[6]. Radhakrishnan, D. (2001). Low-voltage low-power CMOS full adder. IEE Proceedings - Circuits, Devices and Systems, 148(1), 19-24. https://doi.org/10.1049/ip-cds:200 10170

[7]. Timarchi, S., & Navi, K. (2009). Arithmetic circuits of redundant SUT-RNS. IEEE Transactions on Instrumentation and Measurement, 58(9), 2959-2968. https://doi.org/10.1 109/TIM.2009.2016793

[8]. Wang, L., & Shanbhag, N. R. (1999, May). Noisetolerant dynamic circuit design. In 1999, IEEE International Symposium on Circuits and Systems (ISCAS) (Vol. 1, pp. 549- 552). IEEE. https://doi.org/10.1109/ISCAS.1999.777950

[9]. Weste, N. H., & Harris, D. (2015). CMOS VLSI Design: A Circuits and Systems Perspective. Pearson Education India.

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Research Paper

Modeling and Control of UPFC for Power Flow Management

P. V. Sawant* , B. D. Todankar, D. S. Mhapsekar*, P. M. Thakur**, S. M. Waingankar*, S. S. Wamane****

- Department of Electrical Engineering, SSPM College of Engineering, Kanakavli, Maharashtra, India.

** Department of Electrical Engineering, Finolex Academy of Management and Technology, Ratnagiri, Maharashtra, India.

Sawant, P. V., Todankar, B. D., Mhapsekar, D. S., Thakur, P. M., Waingankar, S. M., and Wamane, S. S. (2021). Modeling and Control of UPFC for Power Flow Management. i-manager's Journal on Circuits and Systems, 9(2), 30-38. https://doi.org/10.26634/jcir.9.2.15321

Abstract

This study discusses the Unified Power Flow Controller (UPFC) to improve power system voltage stability. With its unique ability to manage parallel flows of real and reactive power on a transmission line, as well as adjust the voltage on the bus, where it affects the stability of the power system. This will provide much-needed flexibility to power system operators to meet the requirements that the deregulated power system would impose. The shunt converter regulates the transmission line reactive power flow and the DC link voltage in UPFC's fundamental control approach. The series converter controls the actual power flow in the transmission line as well as the UPFC bus voltages. The performance of UPFC to regulate the flow of power across the transmission line is examined in this research. Real power, reactive power, and voltage over the transmission line cannot be managed without UPFC. The UPFC circuit model is created in MATLAB/Simulink utilizing rectifier and inverter circuits, and simulation results are shown to verify the model.

References

[1]. Ambriz-Perez, H., Acha, E., Fuerte-Esquivel, C. R., & De la Torre, A. (1998). Incorporation of a UPFC model in an optimal power flow using Newton's method. IEE Proceedings - Generation, Transmission and Distribution, 145(3), 336-344. https://doi.org/10.1049/ip-gtd:19981944

[2]. Edris, A., Mehraban, A. S., Rahman, M., Gyugyi, L., Arabi, S., & Reitman, T. (1998). Controlling the flow of real and reactive power. IEEE Computer Applications in power, 11(1), 20-25. https://doi.org/10.1109/67.648493

[3]. Fuerte-Esquivel, C. R., & Acha, E. (1996). Newton- Raphson algorithm for the reliable solution of large power networks with embedded FACTS devices. IEE Proceedings- Generation, Transmission and Distribution, 143(5), 447- 454. https://doi.org/10.1049/ip-gtd:19960531

[4]. Gyugyi, L. (1992, July). Unified power-flow control concept for flexible AC transmission systems. In IEE Proceedings C (Generation, Transmission and Distribution), 139(4), 323-331. https://doi.org/10.1049/ip-c.1992.0048

[5]. Hingorani, N. G., Gyugyi, L., & El-Hawary, M. (2000). Understanding FACTS: Concepts and technology of flexible AC transmission systems (Vol. 1). New York: IEEE Press.

[6]. Nabavi-Niaki, A., & Iravani, M. (1996). Steady-state and dynamic models of unified power flow controller (UPFC) for power system studies. IEEE Transactions on Power Systems, 11(4), 1937-1943. https://doi.org/10.1109/59.54 4667

[7]. Noroozian, M., Angquist, L., Ghandhari, M., & Andersson, G. (1997). Use of UPFC for optimal power flow control. IEEE Transactions on Power Delivery, 12(4), 1629- 1634. https://doi.org/10.1109/61.634183

[8]. Park, J. S., Jang, G. S., & Son, K. M. (2008). Modeling and control of VSI type FACTS controllers for power system dynamic stability using the current injection method. International Journal of Control, Automation, and Systems, 6(4), 495-505.

[9]. Round, S. D., Yu, Q., Norum, L. E., & Undeland, T. M. (1996). Performance of a unified power flow controller using a d-q control system. In Sixth International Conference on AC and DC Power Transmission (pp. 357–362). https://doi.org/10.1049/cp:19960384

i-manager's Journal on Circuits and Systems (JCIR)

Current Issue Vol. 11 Issue 2

Most Read

Most Cited

Volume 9 Issue 2 July - December 2021

Power and Ground Bounce Reduction Techniques for Nanoscale VLSI Systems

M. Kavitha*

Department of Electronics and Communication Engineering, Government College of Engineering, Bargur, Tamilnadu, India.

Kavitha, M. (2021). Power and Ground Bounce Reduction Techniques for Nanoscale VLSI Systems. i-manager's Journal on Circuits and Systems, 9(2), 1-8. https://doi.org/10.26634/jcir.9.2.18473

Abstract

References

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Implementation of Seven-Level Reversing Voltage Inverter using Multi Reference Based Space Vector PWM Technique

S. Nagaraja Rao* , D. V. Ashok Kumar**, CH. Sai Babu***

*-***Department of Electrical and Electronics Engineering, Jawaharlal Nehru Technological University, Kakinada, Andhra Pradesh, India.

Rao, S. N., Kumar, D. V. A., and Babu, C. H. S. (2021). Implementation of Seven-Level Reversing Voltage Inverter using Multi Reference Based Space Vector PWM Technique. i-manager's Journal on Circuits and Systems, 9(2), 9-15. https://doi.org/10.26634/jcir.9.2.15789

Abstract

References

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Implementation of Pipelined ADC using 22 nm FinFET Technology

M. Chandra Sekhar Reddy*

Department of Electronics and Communication Engineering, Sree Vidyanikethan Engineering College, Tirupati, Andhra Pradesh, India.

Reddy, M. C. S. (2021). Implementation of Pipelined ADC using 22 nm FinFET Technology. i-manager's Journal on Circuits and Systems, 9(2), 16-22. https://doi.org/10.26634/jcir.9.2.15094

Abstract

References

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Design and Implementation of Low Power and High-speed Braun Multiplier using Hybrid Full Adder

I. Omesh* , B. Supriya**, Carol Schubert***, A. Likitha****, D. Aditya*****

*-***** Department of Electronics and Communication Engineering, Lendi Institute of Engineering and Technology, Vizianagaram, Andhra Pradesh, India.

Omesh, I., Supriya, B., Yamini, Y., Likitha, A., and Aditya, D. (2021). Design and Implementation of Low Power and Highspeed Braun Multiplier using Hybrid Full Adder. i-manager's Journal on Circuits and Systems, 9(2), 23-29. https://doi.org/10.26634/jcir.9.2.16831

Abstract

References

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Modeling and Control of UPFC for Power Flow Management

P. V. Sawant* , B. D. Todankar**, D. S. Mhapsekar***, P. M. Thakur****, S. M. Waingankar*****, S. S. Wamane******

*-***** Department of Electrical Engineering, SSPM College of Engineering, Kanakavli, Maharashtra, India. ****** Department of Electrical Engineering, Finolex Academy of Management and Technology, Ratnagiri, Maharashtra, India.

Sawant, P. V., Todankar, B. D., Mhapsekar, D. S., Thakur, P. M., Waingankar, S. M., and Wamane, S. S. (2021). Modeling and Control of UPFC for Power Flow Management. i-manager's Journal on Circuits and Systems, 9(2), 30-38. https://doi.org/10.26634/jcir.9.2.15321

Abstract

References

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S. Nagaraja Rao* , D. V. Ashok Kumar, CH. Sai Babu*

I. Omesh* , B. Supriya, Carol Schubert, A. Likitha, D. Aditya

P. V. Sawant* , B. D. Todankar, D. S. Mhapsekar*, P. M. Thakur**, S. M. Waingankar*, S. S. Wamane****

- Department of Electrical Engineering, SSPM College of Engineering, Kanakavli, Maharashtra, India.

** Department of Electrical Engineering, Finolex Academy of Management and Technology, Ratnagiri, Maharashtra, India.