References
[1]. Abo, A. M., & Gray, P. R. (1999). A 1.5-V, 10-bit, 14.3-MS/s
CMOS pipeline analog-to-digital converter. IEEE Journal of
Solid-State Circuits, 34(5), 599-606. https://doi.org/10.110
9/4.760369
[2]. Baker, R. J. (2011). CMOS: Circuit Design, Layout, and
Simulation. John Wiley & Sons.
[3]. Duarte, J. P., Paydavosi, N., Venugopalan, S., Sachid,
A., & Hu, C. (2013, September). Unified FinFET compact
model: modelling trapezoidal triple-gate FinFETs. In 2013,
International Conference on Simulation of Semiconductor Processes and Devices (SISPAD) (pp. 135-138). IEEE. https://
doi.org/10.1109/SISPAD.2013.6650593
[4]. Oskuii, S. T. (2004). Comparative study on low-power
high-performance flip-flops (Dissertation). Department of
Electrical Engineering, Linköping University, Sweden.
[5]. Rahou, F. Z., Guen-Bouazza, A., & Rahou, M. (2013).
Electrical characteristics comparison between fullydepleted
SOI MOSFET and partially-depleted SOI MOSFET
using Silvaco software. Global Journal of Research in
Engineering, 13(1), 1-6.
[6]. Rai, A., & Venkatesan, B. A. (2014). Analysis and design
of high speed low power comparator in ADC. International
Journal of Engineering Development and Research
(IJEDR), 2(1), 1015- 1020.
[7]. Reyes, B. T., Biolato, L., Galetto, A. C., Passetti, L., Solis,
F., & Hueda, M. R. (2019). An energy-efficient hierarchical
architecture for time-interleaved SAR ADC. IEEE
Transactions on Circuits and Systems I: Regular Papers,
66(6), 2064-2076. https://doi.org/10.1109/TCSI.2019.2901
795
[8]. Rossi, A., & Fucili, G. (1996). Nonredundant successive
approximation register for A/D converters. Electronics
Letters, 32(12), 1055-1057.
[9]. Sowmya, T., Nihal, S. M., & Chand, D. G. (2018).
Implementation of 16-bit pipelined ADC using 180 nm
CMOS technology. International Research Journal of
Engineering and Technology, 5(3), 591-595.
[10]. Tual, S. L., Singh, P. N., Curis, C., & Dautriche, P. (2014,
February). 22.3 A 20GHz-BW 6b 10GS/s 32mW timeinterleaved
SAR ADC with Master T&H in 28nm UTBB FDSOI technology. In 2014, IEEE International Solid-State Circuits
Conference Digest of Technical Papers (ISSCC) (pp. 382-
383). IEEE. https://doi.org/10.1109/ISSCC.2014.6757479
[11]. Yee, Y. S., Terman, L. M., & Heller, L. G. (1979). A twostage
weighted capacitor network for D/A-A/D conversion.
IEEE Journal of Solid-State Circuits, 14(4), 778-781.
https://doi.org/10.1109/JSSC.1979.1051264
