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i-manager's Journal on Circuits and Systems (JCIR)

Current Issue Vol. 11 Issue 2

Voltage Stability and Power Loss Minimization with UPFC using Heuristic and Hybrid Heuristic Methods
Design and Analysis of Voltage Difference Transconductance Amplifier (VDTA) at FINFET CMOS Technology
Efficient Logic Cell Design for Ultralow-Energy Subthreshold Operation in Wearable Biomedical Systems
Design and Optimization of MSI-Enabled Multi-Precision Binary Multiplier Architecture
Analysis of Carbon Nanotube for Low Power Nano Electronics Applications

Most Cited

Volume 7 Issue 4 September - November 2019

Research Paper

Analysis, Design and Performance Comparison of Strongarm Latch Comparator

G. Appala Naidu* , N. Maheswari**

* Department of Systems and Signal processing, JNTUK-University College of Engineering, Vizianagaram, Andha Pradesh, India.

** Department of Electronics and Communication Engineering, JNTUK-University College of Engineering, Vizianagaram, Andha Pradesh, India.

Maheswari, N., and Naidu, G. A. (2019). Analysis, Design and Performance Comparison of Strongarm Latch Comparator. i-manager's Journal on Circuits and Systems , 7(4), 1-9. https://doi.org/10.26634/jcir.7.4.17110

Abstract

Digital signals are crucial for transmission of information easily and securely. In digital scenario, Analog to Digital Converters (ADC) are essential for applications such as wireless communication and signal processing. Designing low power circuits that operate at low supply voltages operating at high speed plays an important role in VLSI. Among these circuits comparator is one. Comparators with high-speed, low power and reduced delay are important for faster operations in ADC. This paper presents the design of an improved Strong ARM latch comparator by reducing delay time for enhancing its speed of operation. Comparative analysis for proposed design in terms of various parameters including power, energy per conversion, delay, speed, offset and power-delay product are presented. Delay Comparison for different dynamic comparators are performed. The standard deviation of the input-referred offset for proposed design is 8.81mV at 1V supply. The proposed dynamic comparator is faster and consumes less power. At a clock frequency of 0.2 GHz and 1 mV.

References

[1]. Babayan-Mashhadi, S., & Lotfi, R. (2013). Analysis and design of a low-voltage low-power double-tail comparator. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 22(2), 343-352. https://doi.org/ 10.1109/TVLSI.2013.2241799

[2]. Bindra, H. S., Lokin, C. E., Schinkel, D., Annema, A. J., & Nauta, B. (2018). A 1.2-V dynamic bias latch-type comparator in 65-nm CMOS with 0.4-mV input noise. IEEE Journal of Solid-State Circuits, 53(7), 1902-1912. https://doi.org/10.1109/JSSC.2018.2820147

[3]. Carusone, T. C., Johns, D. A., & Martin, K. W. (2012). Integrated-Circuit Devices and Modeling. Analog Integrated Circuit Design, 2^nd ed., United States: John Wiley & Sons, 42-44.

[4]. Choi, R. Y. K., & Tsui, C. Y. (2012, August). A novel offset cancellation technique for dynamic comparator latch. In 2012, IEEE 55^th International Midwest Symposium on Circuits and Systems (MWSCAS) (pp. 614-617). IEEE. https://doi.org/10.1109/MWSCAS.2012.6292095

[5]. Goll, B., & Zimmermann, H. (2009). A comparator with reduced delay time in 65-nm CMOS for supply voltages down to 0.65 V. IEEE Transactions on Circuits and Systems II: Express Briefs, 56(11), 810-814. https://doi.org/10.1109/ TCSII.2009.2030357

[6]. Hussain, S., Kumar, R., & Trivedi, G. (2017, December). Comparison and design of dynamic comparator in 180nm SCL technology for low power and high speed flash ADC. In 2017, IEEE International Symposium on Nanoelectronic and Information Systems (ISNIS) (pp. 139- 144). IEEE.

[7]. Kim, S. J., Kim, D., & Seok, M. (2017, July). Comparative study and optimization of synchronous and asynchronous comparators at near-threshold voltages. In 2017, IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED) (pp. 1-6). IEEE. https://doi. org/10.1109/ISLPED.2017.8009169

[8]. Kobayashi, T., Nogami, K., Shirotori, T., Fujimoto, Y., & Watanabe, O. (1992, June). A current-mode latch sense amplifier and a static power saving input buffer for lowpower architecture. In 1992, Symposium on VLSI Circuits Digest of Technical Papers (pp. 28-29). IEEE. https://doi.org/10.1109/VLSIC.1992.229252

[9]. Li, Y., Mao, W., Zhang, Z., & Lian, Y. (2014, November). An ultra-low voltage comparator with improved comparison time and reduced offset voltage. In 2014, IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) (pp. 407-410). https://doi.org/10.1109/APCCAS .2014.7032806

[10]. Papadopoulou, A., Milovanović, V., & Nikolić, B. (2017, November). A low-voltage low-offset dual strongarm latch comparator. In 2017 IEEE Asian Solid-State Circuits Conference (A-SSCC) (pp. 281-284). IEEE. https://doi.org/ 10.1109/ASSCC.2017.8240271

[11]. Razavi, B. (2015). The strong ARM latch (a circuit for all seasons). IEEE Solid-State Circuits Magazine, 7(2), 12- 17. https://doi.org/10.1109/MSSC.2015.2418155

[12]. Schinkel, D., Mensink, E., Klumperink, E., Van Tuijl, E., & Nauta, B. (2007, February). A double-tail latch-type voltage sense amplifier with 18ps setup+ hold time. In 2007, IEEE International Solid-State Circuits Conference: Digest of Technical Papers (pp. 314-605). IEEE. https://doi. org/10.1109/ISSCC.2007.373420

[13]. Wang, Y., Yao, M., Guo, B., Wu, Z., Fan, W., & Liou, J. J. (2019). A low-power high-speed dynamic comparator with a transconductance - enhanced latching stage. IEEE Access, 7, 93396-93403. https://doi.org/10.1109/ACCESS .2019.2927514

[14]. Wicht, B., Nirschl, T., & Schmitt-Landsiedel, D. (2004). Yield and speed optimization of a latch-type voltage sense amplifier. IEEE Journal of Solid-State Circuits, 39(7), 1148-1158. https://doi.org/10.1109/JSSC.2004.829399

[15]. Xu, H., & Abidi, A. A. (2019). Analysis and design of regenerative comparators for low offset and noise. IEEE Transactions on Circuits and Systems I: Regular Papers, 66(8), 2817-2830. https://doi.org/10.1109/TCSI.2019.29 09032

[16]. Yazid, M. (2018). Low-noise dynamic comparator circuit with selectable input-referred thermal noise voltage. Electronics Letters, 54(21), 1210-1212. https:// doi.org/10.1049/el.2018.5484

[17]. Ziaei, N. E. (2016). Designing and simulation of low and rapid voltage comparator. IOSR Journal of Electrical and Electronics Engineering, 11(4), 98-108. https://doi. org/10.9790/1676-11040198108

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Research Paper

Improved Feedback Linearization Control Scheme based Direct Power Control for Three-Phase Voltage Source Inverters

Rajesh Khanna Bhuthukuri* , Poonam Upadhyay **

* Department of Electrical & Electronics Engineering, JNT University, Hyderabad, Telangana, India.

** Department of Electrical & Electronics Engineering, VNRVJIET, Hyderabad, Telangana, India.

Bhuthukuri, R. K., and Upadhyay, P. (2019). Improved Feedback Linearization Control Scheme based Direct Power Control for Three-Phase Voltage Source Inverters. i-manager's Journal on Circuits and Systems , 7(4), 10-19. https://doi.org/10.26634/jcir.7.4.16397

Abstract

This paper presents feedback linearization technique based Direct Power Control (DPC) algorithm for 3-phase Voltage Source Inverter (VSI). In order to make the controller design easy and independent of the operating point, the non-linear model of the VSI is transferred into linear model. The Direct Power Control - Space Vector Modulation (DPC-SVM) technique is adopted and the problem is formulated in DPC framework in which the constant switching frequency is maintained throughout the operation of the Inverter. A robust nonlinear controller for DPC-VSI applying Input-Output linearization (IOL) techniques is also discussed. To cancel the non linearities and to decouple the input control variables, the feedback linearization nonlinear technique is used. Great tracking capability with zero steady-state of the voltage loop has been achieved by zero-dynamic control. Also, there is no derivative calculation required and measurement of load current is not needed. The controller which is proposed in this paper has advantages of fast DC-bus voltage response, robust against parameter uncertainties and decoupled dynamical d-q current loops which provide wide operating range and fast transient responses. The validity of the technique has been verified through experimental setup which is compared with the traditional control. The results analysis shows that the use of feedback linearization control gives excellent transient response both during balanced and unbalanced load and with gird voltage.

References

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[2]. Azizi, H., Vahedi, A., & Papi, G. H. (2005). Investigation of power quality disturbance effects on the direct power controlled PWM rectifier. WSEAS Transactions on Systems, 4(10), 1777-1784.

[3]. Carbone, R., & Scappatura, A. (2005). An improved three-phase rectifier for PWM adjustable speed drives with passive power factor correction and resistance emulation. WSEAS Transactions on Circuits and Systems, 4(8), 952-959.

[4]. Du, C., Agneholm, E., & Olsson, G. (2009). VSC-HVDC system for industrial plants with onsite generators. IEEE Transactions on Power Delivery, 24(3), 1359-1366. https://doi.org/10.1109/TPWRD.2009.2013384

[5]. Duarte-Mermoud, M. A., Estrada, J. L., & Travieso- Torres, J. C. (2006). Model reference adaptive control of linear time-varying plants. WSEAS Transactions on Circuits and Systems, 5(4), 457-464.

[6]. Gonzalez-Hernandez, S., Moreno-Goytia, E., Martinez-Cardenas, F., & Anaya-Lara, O. (2008, September). Analysis of integrated wind farm using a multiterminal VSC-HVDC: Different electrical conditions response. In 2008, 40^th North American Power Symposium (pp.1-5).IEEE. https://doi.org/10.1109/NAPS. 2008.5307391

[7]. Guedouani, R., Fiala, B., Berkouk, E. M., & Boucherit, M. S. (2007). A new algorithm control for three-phase AC/DC pulse widthmodulation voltage source rectifier. WSEAS Transactions on Circuits and Systems, 6(1), 102- 109.

[8]. Guo-Qiang, W., & Zhi-Xin, W. (2010). Control of HVDClight transmission for offshore wind farms based on inputoutput feedback linearization and PSO. WSEAS Transactions on Systems, 9(11), 1109-1119.

[9]. Isidori, A. (1989). Nonlinear Control Systems, Berlin, Germany: Springer-Verlag.

[10]. Jeong, S. J., & Song, S. H. (2007). Improvement of predictive current control performance using online parameter estimation in phase controlled rectifier. IEEE Transactions on Power Electronics, 22(5), 1820-1825. https://doi.org/10.1109/TPEL.2007.904235

[11] Koytiva, X., Vrionis,T., Vovos, N.A.,& Giannakopoulos, G. B. (2005). Application of adaptive fuzzy control for the mitigation of fault disturbances in an HVDC link based on VSCs. WSEAS Transactions on Systems, 4(8), 1354-1362.

[12]. Lee, D. C. (2000). Advanced nonlinear control of three-phase PWM rectifiers. IEE Proceedings-Electric Power Applications, 147(5), 361-366. https://doi.org/10. 1049/ip-epa:20000621

[13]. Lee, D. C., Lee, G. M., & Lee, K. D. (2000). DC-bus voltage control of three-phase AC/DC PWM converters using feedback linearization. IEEE Transactions on Industry Applications, 36(3), 826-833. https://doi.org/ 10.1109/28. 845058

[14]. Lee, T. S. (2003). Input-output linearization and zerodynamics control of three-phase AC/DC voltage-source converters. IEEE Transactions on Power Electronics, 18(1), 11-22. https://doi.org/10.1109/TPEL.2002.807145

[15]. Lu, W., & Ooi, B. T. (2003). DC overvoltage control during loss of converter in multiterminal voltage-source converter-based HVDC (M-VSC-HVDC). IEEE Transactions on Power Delivery, 18(3), 915-920. https://doi.org/ 10.1109/TPWRD.2003.813888

[16]. Malinowski, M., Jasinski, M., & Kazmierkowski, M. P. (2004). Simple direct power control of three-phase PWM rectifier using space-vector modulation (DPC-SVM). IEEE Transactions on Industrial Electronics, 51(2), 447-454. https://doi.org/10.1109/TIE.2004.825278

[17]. Malinowski, M., Kazmierkowski, M. P., Hansen, S., Blaabjerg, F., & Marques, G. D. (2001). Virtual-flux-based direct power control of three-phase PWM rectifiers. IEEE Transactions on Industry Applications, 37(4), 1019-1027. https://doi.org/10.1109/28.936392

[18]. Marzouki, A., Hamouda, M., & Fnaiech, F. (2010, July). Sensorless nonlinear control for a three-phase PWM AC-DC converter. In 2010. IEEE International Symposium on Industrial Electronics (pp. 1052-1057). IEEE. https://doi.org/10.1109/ISIE.2010.5636919

[19]. Niculescu, E., Iancu, E. P., Niculescu, M. C., & Purcaru, D. M. (2006, September). Analysis of PWM converters using MATLAB. In Proceedings of the 6^th WSEAS International Conference on Simulation, Modelling and Optimization, 507-512.

[20]. Noguchi, T., Tomiki, H., Kondo, S., & Takahashi, I. (1998). Direct power control of PWM converter without power-source voltage sensors. IEEE Transactions on Industry Applications, 34(3), 473-479. https://doi.org/ 10.1109/28.673716

[21]. Petrzela, J. H., & Hrubos, Z. (2009, October). Simplest Chaos Converters: Modeling, Analysis and Future Perspectives. In Proceedings of the 8^th WSEAS International Conference on System Science and Simulation in Engineering (pp. 160-163).

[22]. Phruksarangruk, T., & Nungam, S. A. (2015). Novel Control of Three Phase Converters using Feedback Linearization Technique. In Proceedings of the 7^thConference of Electrical Engineering Network, of Rajamangala University of Technology.

[23]. Rafiei, M., Ghazi, R., Asgharian, R., Toliyat, H. A., & Barakati, M.(2006, August). Robust control methodologies for dc/dc PWM converters under wide changes in operating conditions. In Proceedings of the 6^th WSEAS International Conference on Systems Theory & Scientific Computation (pp. 200-210).

[24]. Slotine, J. J. E., & Li, W. (1991). Applied Nonlinear Control, Englewood Cliffs. NJ: Prentice-Hall.

[25]. Suh, Y., Tijeras, V., & Lipo, T. A. (2002, October). A nonlinear control of the instantaneous power in DQ synchronous frame for PWM AC/DC converter under generalized unbalanced operating conditions. In Conference Record of the 2002 IEEE Industry th Applications Conference. 37 IAS Annual Meeting (Cat. No. 02CH37344) (Vol. 2, pp. 1189-1196). IEEE. https://doi.org/ 10.1109/IAS.2002.1042709

[26]. Wang, F. (2002). Sine-triangle versus space-vector modulation for three-level PWM voltage-source inverters. IEEE Transactions on Industry Applications, 38(2), 500-506. https://doi.org/10.1109/28.993172

[27]. Zhou, K., & Wang, D. (2002). Relationship between space-vector modulation and three-phase carrier-based PWM: A comprehensive analysis [three-phase inverters]. IEEE Transactions on Industrial Electronics, 49(1), 186-196. https://doi.org/10.1109/41.982262

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Research Paper

Implementation of Power Reduction in CMOS Circuits

D. Suresh Kumar* , K. Rajasekhar **

* Department of Electronics and Communication Engineering, Lendi Institute of Engineering and Technology, Jonnada, Andhra Pradesh, India.

** Department of Electronics and Communication Engineering, Baba institute of Technology & Sciences, Visakhapatnam, Andhra Pradesh, India.

Kumar, D. S., and Rajasekhar, K. (2019). Implementation of Power Reduction in CMOS Circuits. i-manager's Journal on Circuits and Systems , 7(4), 20-26. https://doi.org/10.26634/jcir.7.4.16832

Abstract

In recent trends, the industry and most researchers are focusing on the scale down of CMOS technologies to improve the speed and leakage power reduction in the circuits. These unsought leakage currents should be minimized for smooth functioning of the circuits. To develop such type of leakage-free CMOS circuits could be challenging. The main objective of the project is to address the issues over leakage power reductions, delay and efficiency. We present a circuit technique for mitigating MOSFET through controlling the voltage at source terminal of the MOSFET. In this paper we will present CMOS INVERTER, NAND, NOR, XOR using Lector technique. The simulation results are obtained with the aid of MENTOR GRAPHICS of 120 nm technology and also the comparisons of power dissipation by using with and without Lector techniques and with other techniques.

References

[1]. ASIC-SoC on Chip. (n.d.). Low Power VLSI Design and Implementation: Tutorials. Retrieved from https://asicsoc. blogspot.com/p/low-power vlsi.html

[2]. Chowdhury, A. J., Rizwan, M. S., Nibir, S. J., & Siddique, M. R. A. (2012, December). A new leakage reduction method for ultra low power VLSI design for portable devices. In 2012, 2^nd International Conference on Power, Control and Embedded Systems (pp. 1-4). IEEE. https://doi.org/10.1109/ICPCES.2012.6508074

[3]. Dilip, B., Prasad, P. S., & Bhavani, R. S. G. (2012). Leakage power reduction in CMOS circuits using leakage control transistor technique in nanoscale technology. International Journal of Electronics Signals and Systems (IJESS), 2(1), 72-77.

[4]. Gangele, M., & Patra, K. P. (2015). Comparative Analysis of LECTOR and Stack Technique to reduce the leakage current in CMOS circuits. International Journal of Research in Engineering and Technology, 4(7), 92-100.

[5]. Ghosh, D., Guha, J., De, A., & Mukharjee, A. (2013). Power reduction in modern VLSI circuit: A Review. International Journal of Student Reasearch Technology and Management, 1(4).

[6]. Goankar, S. (2015). Design of CMOS inverter using LECTOR Technique to reduce the leakage power. International Journal of Recent Technology and Engineering, Special, 31, 231-233.

[7]. Maheswari, V. (n.d.). Leakage Power Reduction Techniques in CMOS VLSI Circuits (Slides) Retrieved from https://Slideshare.net/vivekmaheswari397/leakagepower

[8]. Nandyala, V. R., & Mahapatra, K. K. (2016, January). A Circuit Technique for Leakage Power reduction in CMOS VLSI circuits. In 2016. International Conference on VLSI Systems, Architectures, Technology and Applications (VLSI-SATA) (pp. 1-5). IEEE. https://doi.org/10.1109/VLSISATA. 2016.7593044

[9]. Prasad, D. K., & Shyamala, K. (2014). VLSI Design Black Book. New Delhi, India:Wiley.

[10]. Ray, K. B., Mandal, S. K., & Patro, B. S. (2016). Low Power FGSRAM Cell Using Sleepy and LECTOR Technique. Indonesian Journal of Electrical Engineering and Computer Science, 4(2), 333-340.

[11]. Saxena, N., & Soni, S. (2013). Leakage current reduction in CMOS circuits using stacking effect. International Journal of Application or Innovation in Engineering & Management, 2(11), 213-216.

[12]. Verma, P., Sharma, A. K., Pandey, V. S., Noor, A., & Tanwar, A. (2016). Estimation of leakage power and delay in CMOS circuits using parametric variation. Perspectives in Science, 8, 760-763. https://doi.org/10.1016/j.pisc. 2016.06.081

[13]. Yang, L. T., Guo, G.R., Jha N.K. (Eds). (2004). Proceedings of Embedded and Ubiquitous Computing. In Lecture Notes in Computer Science, Vol 3207. Springer.

[14]. Yeo, K. S., & Roy, K. (2009). Low voltage, Low Power VLSI Subsystems. Tata McGraw Hill Education.

[15]. Yousif, S. M., Sidek, R. M., Mekki, A. S., Sulaiman, N., & Varahram, P. (2016). Efficient Low-Complexity Digital Predistortion for Power Amplifier Linearization. International Journal of Electrical and Computer Engineering, 6(3), 1096-1105. https://doi.org/ 10.11591/ ijece.v6i3.10328

[16]. Zhigang, Z., Jingqin, W., Li, W., & Meng, W. (2017). Reliability Evaluation of Low-voltage Switchgear Based on Maximum Entropy Principle. Telkomnika, 15(1), 101-108.

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Research Paper

FPGA Implementation Radix-2 Architecture For Twin Data

V. Nancharaiah * , B. Sridhar , Indira. S *

*-*** Department of Electronics and Communication Engineering, Lendi Institute of Engineering and Technology, Vizianagaram, India.

Nanchariah, V., Sridhar, B., and Indira, S. (2019). FPGA Implementation Radix-2 Architecture For Twin Data. i-manager's Journal on Circuits and Systems , 7(4), 27-37. https://doi.org/10.26634/jcir.7.4.17453

Abstract

The fundamental operation in digital signal processing and wireless signal processing applications like Multiple Input and Multiple Output (MIMO), Orthogonal Frequency Division Multiple Access (OFDM) is a Fast Fourier Transform(FFT). FFT is the fastest way of computing Discrete Fourier Transform by way of Divide and Conquer technique. There are different ways of developing VLSI architecture for FFT processor by using Delay elements (SDF, MDF), Delay Commutators (SDC, MDC). The famous architecture for FFT processor is Single Delay Feedback (SDF) architecture which has an advantage of full (100%) hardware utilization. Another famous architecture known as Multipath Delay Commutator (MDC) has an advantage high throughput at 50% of hardware utilization. In this project, we propose VLSI hardware architecture for twin data stream processing using Radix-2 algorithm. The proposed architecture is based on pipelined MDC architecture. The proposed architecture uses both Decimation-In-Time FFT (DIT-FFT) and Decimation-In-Frequency FFT (DIF-FFT) to process even and odd samples of twin data streams. In this architecture the bit reversal operation is carried out by the proposed architecture itself. When compare to other exiting architecture to proposed work designed with shift registers, bit reverserval operation performed in FFT with a high throughput and less numbers of registers.

References

[1]. Cho, S. I., & Kang, K. M. (2010). A Low Complexity 128 Point Mixed Radix FFT Processor for MB OFDM UWB Systems. ETRI Journal, 32(1), 1-10. https://doi.org/10.4218/etrij.10. 0109.0232

[2]. Cooley, J. W., & Tukey, J. W. (1965). An algorithm for the machine calculation of complex Fourier series. Mathematics of computation, 19(90), 297-301. https:// doi.org/10.2307/2003354

[3]. Cortés, A., Vélez, I., & Sevillano, J. F. (2009). Radix $ r $ FFTs: Matricial representation and SDC/SDF pipeline implementation. IEEE transactions on Signal Processing, 57(7), 2824-2839. https://doi.org/10.1109/TSP.2009.2016 276

[4]. Glittas, A. X., Sellathurai, M., & Lakshminarayanan, G. (2016). A normal I/O order radix-2 FFT architecture to process twin data streams for MIMO. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 24(6), 2402- 2406.

[5]. He, S., & Torkelson, M. (1996, April). A new approach to pipeline FFT processor. In Proceedings of International Conference on Parallel Processing, (pp. 766-770). IEEE. https://doi.org/10.1109/IPPS.1996.508145

[6]. He, S., & Torkelson, M. (1998, October). Designing pipeline FFT processor for OFDM (de) modulation. In 1998 URSI International Symposium on Signals, Systems, and Electronics. Conference Proceedings (Cat. No. 98EX167) (pp. 257-262). IEEE. https://doi.org/10.1109/ISSSE.1998. 738077

[7]. Jiang, R. M. (2007). An area-efficient FFT architecture for OFDM digital video broadcasting. IEEE Transactions on Consumer Electronics, 53(4), 1322-1326. https://doi.org/ 10.1109/TCE.2007.4429219

[8]. Jung, Y., Yoon, H., & Kim, J. (2003). New efficient FFT algorithm and pipeline implementation results for OFDM/DMT applications. IEEE Transactions on Consumer Electronics, 49(1), 14-20. https://doi.org/10.1109/TCE. 2003.1205450

[9]. Lin, C. T., Yu, Y. C., & Van, L. D. (2006, May). A lowpower 64-point FFT/IFFT design for IEEE 802.11 a WLAN application. In 2006, IEEE International Symposium on Circuits and Systems (pp. 4-pp). IEEE. https://doi.org/ 10.1109/ISCAS.2006.1693635

[10]. Oh, J. Y., & Lim, M. S. (2005). New radix-2 to the 4 power pipeline FFT processor. IEICE transactions on electronics, 88(8), 1740-1746. https://doi.org/10.1093/ ietele/e88-c.8.1740

[11]. Peng, S. Y., Shr, K. T., Chen, C. M., & Huang, Y. H. (2010, June). Energy-efficient 128∼ 2048/1536-point FFT processor with resource block mapping for 3GPP-LTE system. In Proceedings of International Conference on Green Circuits System (pp. 14-17). https://doi.org/10. 1109/ICGCS.2010.5543106

i-manager's Journal on Circuits and Systems (JCIR)

Current Issue Vol. 11 Issue 2

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Volume 7 Issue 4 September - November 2019

Analysis, Design and Performance Comparison of Strongarm Latch Comparator

G. Appala Naidu* , N. Maheswari**

* Department of Systems and Signal processing, JNTUK-University College of Engineering, Vizianagaram, Andha Pradesh, India. ** Department of Electronics and Communication Engineering, JNTUK-University College of Engineering, Vizianagaram, Andha Pradesh, India.

Maheswari, N., and Naidu, G. A. (2019). Analysis, Design and Performance Comparison of Strongarm Latch Comparator. i-manager's Journal on Circuits and Systems , 7(4), 1-9. https://doi.org/10.26634/jcir.7.4.17110

Abstract

References

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Improved Feedback Linearization Control Scheme based Direct Power Control for Three-Phase Voltage Source Inverters

Rajesh Khanna Bhuthukuri* , Poonam Upadhyay **

* Department of Electrical & Electronics Engineering, JNT University, Hyderabad, Telangana, India. ** Department of Electrical & Electronics Engineering, VNRVJIET, Hyderabad, Telangana, India.

Bhuthukuri, R. K., and Upadhyay, P. (2019). Improved Feedback Linearization Control Scheme based Direct Power Control for Three-Phase Voltage Source Inverters. i-manager's Journal on Circuits and Systems , 7(4), 10-19. https://doi.org/10.26634/jcir.7.4.16397

Abstract

References

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Implementation of Power Reduction in CMOS Circuits

D. Suresh Kumar* , K. Rajasekhar **

* Department of Electronics and Communication Engineering, Lendi Institute of Engineering and Technology, Jonnada, Andhra Pradesh, India. ** Department of Electronics and Communication Engineering, Baba institute of Technology & Sciences, Visakhapatnam, Andhra Pradesh, India.

Kumar, D. S., and Rajasekhar, K. (2019). Implementation of Power Reduction in CMOS Circuits. i-manager's Journal on Circuits and Systems , 7(4), 20-26. https://doi.org/10.26634/jcir.7.4.16832

Abstract

References

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FPGA Implementation Radix-2 Architecture For Twin Data

V. Nancharaiah * , B. Sridhar **, Indira. S ***

*-*** Department of Electronics and Communication Engineering, Lendi Institute of Engineering and Technology, Vizianagaram, India.

Nanchariah, V., Sridhar, B., and Indira, S. (2019). FPGA Implementation Radix-2 Architecture For Twin Data. i-manager's Journal on Circuits and Systems , 7(4), 27-37. https://doi.org/10.26634/jcir.7.4.17453

Abstract

References

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* Department of Systems and Signal processing, JNTUK-University College of Engineering, Vizianagaram, Andha Pradesh, India.

** Department of Electronics and Communication Engineering, JNTUK-University College of Engineering, Vizianagaram, Andha Pradesh, India.

* Department of Electrical & Electronics Engineering, JNT University, Hyderabad, Telangana, India.

** Department of Electrical & Electronics Engineering, VNRVJIET, Hyderabad, Telangana, India.

* Department of Electronics and Communication Engineering, Lendi Institute of Engineering and Technology, Jonnada, Andhra Pradesh, India.

** Department of Electronics and Communication Engineering, Baba institute of Technology & Sciences, Visakhapatnam, Andhra Pradesh, India.

V. Nancharaiah * , B. Sridhar , Indira. S *