Implementation of Power Reduction in CMOS Circuits

D. Suresh Kumar*, K. Rajasekhar **
* Department of Electronics and Communication Engineering, Lendi Institute of Engineering and Technology, Jonnada, Andhra Pradesh, India.
** Department of Electronics and Communication Engineering, Baba institute of Technology & Sciences, Visakhapatnam, Andhra Pradesh, India.
Periodicity:September - November'2019
DOI : https://doi.org/10.26634/jcir.7.4.16832

Abstract

In recent trends, the industry and most researchers are focusing on the scale down of CMOS technologies to improve the speed and leakage power reduction in the circuits. These unsought leakage currents should be minimized for smooth functioning of the circuits. To develop such type of leakage-free CMOS circuits could be challenging. The main objective of the project is to address the issues over leakage power reductions, delay and efficiency. We present a circuit technique for mitigating MOSFET through controlling the voltage at source terminal of the MOSFET. In this paper we will present CMOS INVERTER, NAND, NOR, XOR using Lector technique. The simulation results are obtained with the aid of MENTOR GRAPHICS of 120 nm technology and also the comparisons of power dissipation by using with and without Lector techniques and with other techniques.

Keywords

Power Reduction, CMOS Technologies, Lector Techniques, Power Dissipation.

How to Cite this Article?

Kumar, D. S., and Rajasekhar, K. (2019). Implementation of Power Reduction in CMOS Circuits. i-manager's Journal on Circuits and Systems , 7(4), 20-26. https://doi.org/10.26634/jcir.7.4.16832

References

[1]. ASIC-SoC on Chip. (n.d.). Low Power VLSI Design and Implementation: Tutorials. Retrieved from https://asicsoc. blogspot.com/p/low-power vlsi.html
[2]. Chowdhury, A. J., Rizwan, M. S., Nibir, S. J., & Siddique, M. R. A. (2012, December). A new leakage reduction method for ultra low power VLSI design for portable devices. In 2012, 2nd International Conference on Power, Control and Embedded Systems (pp. 1-4). IEEE. https://doi.org/10.1109/ICPCES.2012.6508074
[3]. Dilip, B., Prasad, P. S., & Bhavani, R. S. G. (2012). Leakage power reduction in CMOS circuits using leakage control transistor technique in nanoscale technology. International Journal of Electronics Signals and Systems (IJESS), 2(1), 72-77.
[4]. Gangele, M., & Patra, K. P. (2015). Comparative Analysis of LECTOR and Stack Technique to reduce the leakage current in CMOS circuits. International Journal of Research in Engineering and Technology, 4(7), 92-100.
[5]. Ghosh, D., Guha, J., De, A., & Mukharjee, A. (2013). Power reduction in modern VLSI circuit: A Review. International Journal of Student Reasearch Technology and Management, 1(4).
[6]. Goankar, S. (2015). Design of CMOS inverter using LECTOR Technique to reduce the leakage power. International Journal of Recent Technology and Engineering, Special, 31, 231-233.
[7]. Maheswari, V. (n.d.). Leakage Power Reduction Techniques in CMOS VLSI Circuits (Slides) Retrieved from https://Slideshare.net/vivekmaheswari397/leakagepower
[8]. Nandyala, V. R., & Mahapatra, K. K. (2016, January). A Circuit Technique for Leakage Power reduction in CMOS VLSI circuits. In 2016. International Conference on VLSI Systems, Architectures, Technology and Applications (VLSI-SATA) (pp. 1-5). IEEE. https://doi.org/10.1109/VLSISATA. 2016.7593044
[9]. Prasad, D. K., & Shyamala, K. (2014). VLSI Design Black Book. New Delhi, India:Wiley.
[10]. Ray, K. B., Mandal, S. K., & Patro, B. S. (2016). Low Power FGSRAM Cell Using Sleepy and LECTOR Technique. Indonesian Journal of Electrical Engineering and Computer Science, 4(2), 333-340.
[11]. Saxena, N., & Soni, S. (2013). Leakage current reduction in CMOS circuits using stacking effect. International Journal of Application or Innovation in Engineering & Management, 2(11), 213-216.
[12]. Verma, P., Sharma, A. K., Pandey, V. S., Noor, A., & Tanwar, A. (2016). Estimation of leakage power and delay in CMOS circuits using parametric variation. Perspectives in Science, 8, 760-763. https://doi.org/10.1016/j.pisc. 2016.06.081
[13]. Yang, L. T., Guo, G.R., Jha N.K. (Eds). (2004). Proceedings of Embedded and Ubiquitous Computing. In Lecture Notes in Computer Science, Vol 3207. Springer.
[14]. Yeo, K. S., & Roy, K. (2009). Low voltage, Low Power VLSI Subsystems. Tata McGraw Hill Education.
[15]. Yousif, S. M., Sidek, R. M., Mekki, A. S., Sulaiman, N., & Varahram, P. (2016). Efficient Low-Complexity Digital Predistortion for Power Amplifier Linearization. International Journal of Electrical and Computer Engineering, 6(3), 1096-1105. https://doi.org/ 10.11591/ ijece.v6i3.10328
[16]. Zhigang, Z., Jingqin, W., Li, W., & Meng, W. (2017). Reliability Evaluation of Low-voltage Switchgear Based on Maximum Entropy Principle. Telkomnika, 15(1), 101-108.
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