i-manager Publications

Design and Validation of Low Power, High Performance Parallel Prefix Adders

Sivadurgarao Parasa*, Paruchuri Naga Venkata Tejaswini**, Mohammad Huzaifa***, Vagu Vardhini****, Pakalapati Geethika*****, Segu Taraka Rama Shanmukh Sai******

*-****** Sasi Institute of Technology and Engineering, Tadepalligudem, Andhra Pradesh, India.

Periodicity:April - June'2025
DOI : https://doi.org/10.26634/jele.15.3.21813

Abstract

In the realm of designing digital systems through Very Large Scale Integration (VLSI), the digital adder takes center stage. However, low-power VLSI adder designs grapple with the Propagation Delay issue, leading to increased latency. This paper explores the viability of Parallel Prefix Adders (PPA) in addressing these challenges for low-power VLSI designs, emphasizing minimal propagation latency. The paper delves into the design and analysis of select PPA models, comparing their performance in terms of area, delay, and power. Utilizing Xilinx Vivado 2019.1, this study evaluates four prominent adders Kogge Stone Adder (KSA), Han Carlson Adder (HCA), Brent Kung Adder (BKA) and Ladner Fischer Adder (LFA) based on key features such as slice count, performance, and power consumption.

Keywords

Kogge-Stone, PDP, Fast Arithmetic, High Performance, Power Optimization.

How to Cite this Article?

Parasa, S., Tejaswini, P. N. V., Huzaifa, M., Vardhini, V., Geethika, P., Sai, S. T. R. S. (2025). Design and Validation of Low Power, High Performance Parallel Prefix Adders. i-manager’s Journal on Electronics Engineering, 15(3), 48-55. https://doi.org/10.26634/jele.15.3.21813

References

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	North Americas,UK, Middle East,Europe		India	Rest of world
	USD	EUR	INR	USD-ROW
Pdf	35	35	200	20
Online	15	15	200	15
Pdf & Online	35	35	400	25

Design and Validation of Low Power, High Performance Parallel Prefix Adders

Abstract

Keywords

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