This paper introduces a novel dynamic comparator design optimized for SAR ADCs, focusing on key advancements in energy efficiency, kickback noise reduction, and speed improvement. The proposed design replaces PMOS transistors with NMOS in the clock path and eliminates the inverter circuit, resulting in substantial reductions in both static and transient power consumption. Through simulations in Cadence Virtuoso (45nm), the design demonstrates significant improvements in transient power, static power, and kickback noise compared to traditional designs. These contributions make the proposed comparator particularly well-suited for energy-efficient, precision-critical applications such as IoT devices, wearables, and biomedical systems. This work marks a significant step toward developing more efficient ADCs for next-generation technologies.