Voltage Stability and Power Loss Minimization with UPFC using Heuristic and Hybrid Heuristic Methods
Design and Analysis of Voltage Difference Transconductance Amplifier (VDTA) at FINFET CMOS Technology
Efficient Logic Cell Design for Ultralow-Energy Subthreshold Operation in Wearable Biomedical Systems
Design and Optimization of MSI-Enabled Multi-Precision Binary Multiplier Architecture
Analysis of Carbon Nanotube for Low Power Nano Electronics Applications
Loss Distribution Methodology with a Sense Of Emission Dispatch
Low Power Optimization Technique Based Linear Feedback Shift Register
Leakage Power Reduction Using Multi Modal Driven Hierarchical Power Mode Switches
Performance of Continuous and Discontinuous Space Vector Pwm Technique for Open End Winding Induction Motor Drive
Validation of IOV chain using OVM Technique
Electronic Circuit Design for Electromagnetic Compliance through Problem-Based Learning
Trioinformatics: The Innovative and Novel Logic Notation That Defines, Explains, and Expresses the Rational Application of The Law of Trichotomy for Digital Instrumentation and Circuit Design
Design Of a Novel Gated 5T SRAM Cell with Low Power Dissipation in Active and Sleep Mode
A Two Stage Power Optimized Implantable Neural Amplifier Based on Cascoded Structures
An Efficient Hybrid PFSCL based Implementation of Asynchronous Pipeline
Present-day power systems have highly complex and stressed operating conditions owing to insufficient reactive power to meet the required power demand. This leads to increased real power and reactive power losses, as well as voltage instability within a power system. To achieve the flexible operation of the power system, Flexible Alternating Current Transmission System (FACTS) devices have been employed. The optimal location of FACTS devices influences the system's performance and significantly affects line/bus reactive power flows. Consequently, the line or bus voltage profiles have been improved, leading to a reduction in power losses. Particle Swarm Optimization (PSO) heuristic methods and HFPSO Hybrid heuristic methods have been used to identify the weakest bus/branch for the suitable placement of UPFC devices, improving voltage stability. This paper discusses a more significant reduction in power losses in a MATLAB environment. Flexible Alternating Current Transmission System (FACTS) devices address reactive power challenges in power systems and enhance operational flexibility. Strategic placement using Particle Swarm Optimization (PSO) and HFPSO Hybrid methods identifies weak points, optimizing Unified Power Flow Controller (UPFC) placement for improved voltage stability. UPFC integration strategically reduces real and reactive power losses, improving power transmission efficiency. This enhances line and bus voltage profiles, addressing instability and significantly reducing overall power losses. The paper offers a detailed analysis of the power system, highlighting the synergy between FACTS devices, heuristic optimization, and power loss reduction. Simulations in MATLAB validate the proposed methodology, demonstrating a noteworthy improvement in power system performance.
This paper proposes a FINFET (Fin Field Effect Transistor)-based Voltage Difference Transconductance Amplifier (VDTA). This paper aims to provide an amplifier that will enable VDTA to achieve its desired characteristics. The circuit proposed for FINFET-based VDTA operates with a bias current order of 150μA and a source voltage of 0.9V. The active element makes the amplitude electronically tuneable with bias current. The designed circuit was implemented in both GPDK 180nm technology and FINFET technology using the Cadence Virtuoso tool. Various factors, including technology node components and the operating voltage provided by FINFET VDTA structures, are compared. A Monte Carlo simulation is conducted for the suggested circuit, which dissipates 187.53μW of power. In comparison to the standard VDTA, it exhibits notably low power dissipation.
This paper explores efficient logic cell design strategies for ultralow-energy subthreshold operation in wearable biomedical systems. Traditional logic cell design approaches often lead to suboptimal efficiency due to unbalanced Pull-Up (PU) and Pull-Down (PD) networks. Various techniques are examined, including balanced PU/PD network design using body biasing and statistical distribution analysis of drain-source current. Moreover, the reverse channel (RSC) effect is investigated for device optimization. Single-stage gates such as inverters, NAND, and NOR gates are designed with Mentor Graphics tools to minimize power dissipation and area. Multistage gates like XOR and XNOR gates are also optimized for reduced signal propagation delay. A detailed analysis of D-flip-flop designs with varying transistor counts is presented. Power dissipation, delay, rise time, and fall time characteristics are compared for flip-flop configurations comprising 18, 10, and 5 transistors. The results indicate significant energy optimization with the proposed designs, particularly with the 5-transistor configuration, demonstrating the effectiveness of the proposed methodologies in achieving superior energy efficiency and reduced signal noise in biomedical systems.
Arithmetic Logic Units (ALUs) are key elements within processors, executing a variety of operations including multiplication, division, addition, and subtraction. Among these, multiplication stands out as the most frequently utilized function within ALUs. This study presents an innovative MSI-interfaced multiplier architecture designed for integration into a multi-precision floating-point multiplier framework. This novel architecture offers configurations for 24-bit, 53-bit, 113- bit, and 237-bit binary operations, corresponding to single, double, quadruple, and octuple precision modes of floating-point computation. Notably, it enhances throughput by accommodating the multiplication of multiple batches of inputs with each operation initiation, surpassing existing binary multiplication systems. A unique Mantissa Similarity Investigation (MSI) implementation is developed and integrated into the binary multiplier architecture. Comparative analysis of the path delay in 24-bit mode against existing 24-bit multipliers demonstrates that the novel MSI-interfaced binary multiplier architecture, with and without MSI, exhibits reduced path delay compared to all existing systems, as anticipated.
In the area of nanotechnology, carbon nanotubes are a notable and remarkable invention. Its structure is much similar to the structure of graphite. CNTs are small in size, light in weight, have good strength, and have good conductivity, making them the building blocks of futuristic new technologies. CNTs have promised to be the catalyst for the next revolution in technology. A broad range of processes are available to produce various types of CNTs, depending on the rolling times of graphite sheets. In this paper, different types of CNTs, their properties, ways of synthesis such as the arc discharge method and chemical vapor deposition, and application have been covered. Outlining their respective advantages and challenges. SWCNTs exhibit high carrier mobilities and tunable bandgaps, making them suitable for transistor devices and interconnects in integrated circuits. DWCNTs offer enhanced mechanical stability and electrical conductivity, catering to applications in flexible electronics and energy storage devices. MWCNTs, though lacking distinct properties of SWCNTs and DWCNTs, find utility in composites, sensors, and biomedical devices due to their ease of synthesis and lower cost.
