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i-manager's Journal on Communication Engineering and Systems (JCS)

Current Issue Vol. 12 Issue 2

Most Cited

Volume 3 Issue 1 November - January 2014

Research Paper

Prioritized PWDEDF Scheduling Algorithm for QoS Enhancement using Network Processor

T. Anna Sudha*

Assistant Professor, Sathyabama University.

Sudha, T. A., (2014). Prioritized PWDEDF Scheduling Algorithm For QoS Enhancement Using Network Processor. i-manager’s Journal on Communication Engineering and Systems, 3(1), 1-8. https://doi.org/10.26634/jcs.3.1.2631

Abstract

The main objective of this paper is to implement the Prioritized Weighted Deficit Earliest Departure First (PWDEDF) scheduling algorithm in a Network Processor (NP) based on router to enhance the multimedia applications. The performance is measured using Network Processor Simulator. The effectiveness of PWDEDF algorithm has been verified by simulations using Intel IXP 2400 NP. Network Processors are emerging as a very promising platform due to their capability of combining the flexibility of General-purpose processors with the high performance of hardware-based solutions. The results shows that, PWDEDF achieves reduction in jitter compared to EDF for different traffic type. Also PWDEDF has 97% less delay compared to EDF (Earliest Deadline First) scheduling algorithm for real time flows.

References

[1]. Deming Liu & Yann-Hang Lee.(2003). An Efficient Scheduling Discipline for Packet Switching Networks using Earliest Deadline First Round Robin. IEEE Department of Computer Science and Engineering. Arizona State University:USA.

[2]. Douglas Corner, Maxim Martynov (2006). Design and Implementation of Hybrid Packet Scheduling Schemes with Network Processors. IEEE ICC Proceedings.

[3]. Golestani.S (1994). A Self Clocked Fair Queuing Scheme for Broadband Applications. In Proc.IEEE INFOCOM’94. (pp. 636-646).Toronto: Ont.Canada.

[4]. Greenberg.A & Madras.N. (1990). How Fair is Fair Queuing?. In Proc.Performance.90

[5]. Jiani Guo,Jingnan Yao & Laxmi Bhuyan(2005). An Efficient Packet Scheduling Algorithm in Network Processors. IEEE.

[6]. John Stankovic. A, Marco Spuri, et al.(1998). Deadline Scheduling for Real-Time systems: EDF and related Algorithms. Kluwer Academic Publishers.

[7]. Parekh.A.K..& Gallager.R.G.(1992). A Generalized Processor sharing approach to flow control. In Proc. IEEE INFOCOM’92.Vol.2, 915-924.

[8]. Ramabhadran. S & Pasquale. J.(2006). The Stratified Round Robin Scheduler: Design, Analysis and Implementation. IEEE/ACM Trans. on Networking. Vol.14. Issue 6.(pp.1362-1373).

[9]. Shreedhar.M & Varghese.G,.(1996). Efficient fair Queuing using Deficit Round Robin. IEEE/ACM Transactions on Networking. Vol.4, No.3.

[10]. Shun Cheng Y & Corneliu Pencea.S.(2002). BSFQ: Bin Sort Fair Queuing. IEEE. Department of Mathematics and Computer Science: Emory University: Atlanta.

[11]. Suri,Varghese.G & Chandranmenon.G. (1997). Leap Forward Virtual Clock: A New Fair Queuing Scheme with Guaranteed Delays and Throughput Fairness, IEEE Infocom (pp.557-565).

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Research Paper

Identification of the Flood Attackers and effective delivery of Packets in Disruption Tolerant Networks

P. S. Nandhini* , P. Suresh**

* Department of Information Technology, Kongu Engineering College.

** Department of Information Technology, Kongu Engineering College.

Nandhini, P. S., and Suresh, P. (2014). Identification of The Flood Attackers and effective Delivery of Packets in Disruption Tolerant Networks. i-manager’s Journal on Communication Engineering and Systems, 3(1), 9-15. https://doi.org/10.26634/jcs.3.1.2632

Abstract

Disruption Tolerant Network (DTN) is a networking architecture that is designed to provide communications in the most unstable and stressed environment. DTN is normally be subjected to frequent disruptions. Due to restriction in network resources such as contact opportunity and buffer space, DTNs are exposed to flood attacks. Flooding is a denial of service attack that is designed to bring a network or service down by flooding it with large amount of traffic. In this paper, limiting the rate is used to be defined against flood attacks in DTNs, so that each node limits the number of packets that can be generated in each time interval and the number of replica that can be generated for each packet. It is a distributed scheme to detect the violation of rate limits. The detection scheme uses claim-carry-and-check mechanism. The structure of the claim adopts the pigeonhole principle to detect the attacker. The detection of the attacker and the efficiency of the proposed scheme are determined using the event driven simulations.

References

[1]. Amin Vahdat and David Becker, "Epidemic Routing for Partially Connected AdHoc Networks?, Technical Report on CS-200006, Duke University, 2000.

[2]. Bryan Parno, Adrian Perrig, and Virgil Gligor (2005). “Distributed Detection of Node Replication Attacks in Sensor Networks? IEEE Symposium on Security and Privacy.

[3]. Feng Li, Avinash Srinivasan, and Jie Wu (2009). “Thwarting Blackhole Attacks in Distruption-Tolerant Networks Using Encounter Tickets,? Proceedings of IEEE INFOCOM.

[4]. Jelena Mirkovic, Seven Dietrich, David Dittrich and Peter Reiher (2005). Internet Denial of Service: Attack and Defense Mechanisms. Prentice Hall.

[5]. Qinghua Li and Guohong Cao (2012). “Mitigating Routing Misbehavior in Disruption Tolerant Networks”, IEEE Transaction on Information Forensics and Security, Vol. 7, No. 2, pp. 664-675, 2012.

[6]. Qinghua Li and Guohong Cao (2012). “Efficient and Privacy-Preserving Data Aggregation in Mobile Sensing”, IEEE International Conference on Network Protocols.

[7]. Qinghua Li, Wei Gao, Sencun Zhu and Guohong Cao (2011). A Routing Protocol for Socially Selfish Delay Tolerant Networks, Ad Hoc Networks, Vol. 10, No. 8, 2011.

[8]. Qinghua Li, Sencun Zhu and Guohong Cao (2010).Routing in Socially Selfish Delay Tolerant Networks, Proceedings of IEEE INFOCOM.

[9]. Vivek Natarajan, Yi Yang and Sencun Zhu (2011). Resource-Misuse Attack Detection in Delay-Tolerant Networks, International Performance of Computing and Communication Conference (IPCCC).

[10]. Yanzhi Ren, Mooi Choo Chuah, Jie Yang and Yingying Chen (2010). Detecting Wormhole Attacks in

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Research Paper

Analysis and Design of Hysteresis Comparator

M. Bharanidharan* , M. Shenbagapriya, N. Santhiyakumari*

* M.E Student, Knowledge Institute of Technology, Salem, India.

Assistant Professor, Department of Electronics and Communication Engineering, Knowledge Institute of Technology, Salem, India.

* Professor and Head, Department of Electronics and Communication Engineering, Knowledge Institute of Technology, Salem, India.

Bharanidharan, M., Shenbagapriya, M., and Santhiyakumari, N. (2014). Analysis and Design of Hysteresis Comparator. i-manager’s Journal on Communication Engineering and Systems, 3(1), 16-21. https://doi.org/10.26634/jcs.3.1.2633

Abstract

The main building block of any portable electronic equipment is the Analog-to-Digital Converter. The increased demand of the portable electronic equipments has forced the circuit designers to use lower supply voltages. However, the performance of analog circuits is degraded at low supply voltage due to large power dissipation and higher noise occurrence. This makes the design of voltage analogue circuits more challenging. As comparator is the basic device of analog to digital converters, this paper aims to analyze the comparator design with hysteresis. This proposed technique reduces the power dissipation and noise. The results were compared with the double tail comparator, which operates with supply voltage of 0.6v.

References

[1]. Samaneh Babayan-Mashhadi & Reza Lotfi. (2013). Analysis and Design of a Low-Voltage Low-Power Double- Tail Comparator.

[2]. S. U. Ay. (2011). A sub-1 volt 10-bit supply boosted SAR ADC design in standard CMOS. Int. J. Analog Integr. Circuits Signal Process, Vol. 66, No. 2, pp. 213–221.

[3]. A. Mesgarani, M. N. Alam, F. Z. Nelson, & S. U. Ay. (2010). Supply boosting technique for designing very low-voltage mixed-signal circuits in standard CMOS in Proc. IEEE Int. Midwest Symp. Circuits Syst.Dig. Tech. Papers, pp. 893–896.

[4]. B. Goll & H. Zimmermann. (2009). A comparator with reduced delay time in 65-nm CMOS for supply voltages down to 0.65 IEEE Trans. Circuits Syst. II, Exp. Briefs, Vol. 56, No. 11, pp. 810–814.

[5]. B. Goll & H. Zimmermann. (2007). Low-power 600MHz comparator for 0.5 V supply voltage in 0.12 ?m CMOS IEEE Electron.Lett., Vol. 43, No. 7, pp. 388–390.

[6]. B. Goll & H. Zimmermann. (2007). A 0.12 ?m CMOS comparator requiring 0.5V at 600MHz and 1.5V at 6 GHz in Proc. IEEE Int. Solid-State Circuits Conf., Dig. Tech. Papers, pp. 316–317.

[7]. P. M. Figueiredo & J. C. Vital. (2006). Kickback noise reduction technique for CMOS latched comparators IEEE Trans. Circuits Syst. II, Exp.Briefs, Vol. 53, No.7,pp. 541–545,

[8]. M. Maymandi-Nejad & M. Sachdev. (2003). 1-bit quantizer with rail to rail Input range for sub-1V ?modulators IEEE Electron. Lett, Vol. 39, No. 12, pp. 894–895.

[9]. B.Razavi & B.A.Wooley. (1992). Design Techniques for High-Speed High-Resolution Comparators IEEE J. Solid- State Circuits, vol. SC-27, pp.1916-1926.

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Research Paper

Vehicle Speed Violation Control and Tracking using GSM

M. Pratheba* , G. Sekhar, K. Sivaprakash*

* Assistant Professor, Department of EEE, SNS College of Engineering

-* PG Scholar, Department of EEE, SNS College of Engineering

Pratheba, M., Sivaprakash, S. K., and Sekhar, G. (2014). Vehicle Speed Violation Control and Tracking Using GSM. i-manager’s Journal on Communication Engineering and Systems, 3(1), 22-27. https://doi.org/10.26634/jcs.3.1.2634

Abstract

Violation of traffic rules is a major problem in the current scenario. This paper mainly deals with the control of rules and regulations in the traffic. The recently developed technologies help us to solve the problem easily and wisely. In this paper, the speed of the rider is monitored. If any violation of rules in speed or rash driving is found, a fine is provided to the rider immediately through a message.

References

[1]. Saif, A.A.; Sammak, H.; Matar, D.; Al- Midani, O.; (2010). Automatic monitoring and speed violation ticket system, IEEE International Conference on Systems Man and Cybernetics (SMC).

[2]. Gogate, C.A.; Sagaidev, B.S.; Vaidyanathan, S.G., (2004). Monitoring and transmission of heavy vehicle parameters using fixed cellular terminal, IEEE 60th Vehicular Technology Conference, VTC2004-Fall, 2004.

[3]. Pathirana, P.N.; Plunkett, T.R.; Sch. of Eng. & Technol., (2005). Deakin Univ., Geelong,Vic., Australia , Speed control rd and policing in a cellular mobile network:SpeedNet, : 3 IEEE International Conference on Industrial Informatics, 2005. INDIN '05. 2005.

[4]. Rahim, H.A.; Ahmad, R.B.; Zain, A.S.M.; Sheikh, U.U.;(2005). Implementation and analysis of integration , GSM/GPRS modem in a TMS320VC6713 digital signal processor for vehicle location, International Conference on, Computer and Communication Engineering (ICCCE).

[5]. Elia Nadira Sabudin,; Siti Zarina Mohd Muji,; Mohd. Helmy Abd Wahab,; Johari,Ayob; Norazman Bin Ghani,; (2008). GSM-based notification speed detection for monitoring purposes, International Symposium on

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Research Paper

Design and Implementation of Reconfigurable Microstrip Antenna

M. Alwin* , P. Jothilakshmi**

* M.E Student, Sri Venkateswara college of Engineering, Chennai.

** Assistant Professor, Department of Electronics and Communication Engineering, Sri Venkateswara college of Engineering, Chennai.

Alwin, M., and Jothilakshmi, P. (2014). Design and Implementation of Reconfigurable Microstrip Antenna. i-manager’s Journal on Communication Engineering and Systems, 3(1), 28-32. https://doi.org/10.26634/jcs.3.1.2635

Abstract

A simple new design of Microstrip Patch Antenna has been designed to tune a set of different discrete frequencies. The frequency variation is achieved by changing the electrically actuated RF switches. The antenna’s operative condition is controlled between different states by biasing. The simulation of the designed antenna is done using Advanced design system and its observed parameters are documented in this paper.

References

[1]. J. Costantine, C. G. Christodoulou, S. E. Barbin (2007). “A New Reconfigurable Multi Band Patch Antenna” Microwave and Optoelectronics Conference, Pages 75-78, Oct 29 to Nov 1.

[2]. Dimitrios E. Anagnostou,GuizhenZheng, Michael T. Chryssomallis, James C. Lyke, George E. Ponchak, John Papapolymerou, Christos G. Christodoulou, (2006). “Design, Fabrication, and Measurements of an RF-MEMSBased Self-Similar Reconfigurable Antenna” IEEE transactions on antennas and propagation, Vol. 54, No. 2.

[3]. JosephA.Zammit and Adrian Muscat (2008). “Tunablemicrostrip antenna using switchable patches” Antennas and Propagation Conference, Loughborough, Pages 233-236, UK.

[4]. M. A. Madi, M. Al-Husseini , A. H. Ramadan,K. Y. Kabalan, and A. El-Hajj, (2012). “A Reconfigurable cedar-shaped microstrip antenna for wireless applications” Progress In Electromagnetics Research C, Vol. 25, 209-221.

[5]. Y. Tawk, M. Al-Husseini, S. Hemmady, A. R. Albrecht, G. Balakrishnan, C. G.Christodoulou, (2010). “Implementation of a Cognitive Radio Front-End Using Optically Reconfigurable Antennas”, Pages 294-297, Electro magnetics in Advanced Applications (ICEAA), 20–24 .

[6]. Wu, C., T. Wang, A. Ren, and D. G. Michelson, (2011). “Implementation of reconfigurable patch antennas using reed switches," IEEE Antennas and Wireless Propagation Letters, Vol. 10.

[7]. XiaotaoCai, Anguo Wang and Weigang Chen, (2011). “A Circular Disc-Shaped Antenna with Frequency and Pattern Reconfigurable Characteristics” Pages1-4, 20-22 April, Microwave Conference Proceedings (CJMW), China- Japan Joint.

[8]. Yuan-hai Yu and Chang-peng. Ji, (2011). “Research of Fractal Technology in the Design of Multi-frequency Antenna”, Pages 1-4, Microwave Conference Proceedings (CJMW), China-Japan Joint.

[9]. Songnan Yang, Chunna Zhang, Helen K. Pan, Aly E. Fathy, and Vijay K. Nair, (2009). “Frequency Reconfigurable Antennas for Multiradio Wireless Platforms”, Vol. 10, Pages 63-83, IEEE microwave magazine.

[11]. Constantine A. Balanis, (2011). Antenna Theory Analysis And Design, Aggarwal printing press.

[12]. J.D. Krauss, (2008). Antenna For All applications, Mcgraw-Hill Education LTD.

[13]. Microstrip antenna Design Handbook by Ramesh Garg, PrakashBhartia, InderBahl, ApisakIttipiboon

[14]. Modern Antenna Design by Thomas A. Milligan

[15]. Antennas: fundamentals, design, measurement by Lamont V. Blake and Maurice W. Long

[16]. Antennas: fundamentals, design, measurement by Lamont V. Blake and Maurice W. Long

[17]. Broadband Microstrip Antenna by Girish Kumar, K.P Ray

[18]. Antenna Engineering Handbook by John L. Volakis

i-manager's Journal on Communication Engineering and Systems (JCS)

Current Issue Vol. 12 Issue 2

Most Read

Most Cited

Volume 3 Issue 1 November - January 2014

Prioritized PWDEDF Scheduling Algorithm for QoS Enhancement using Network Processor

T. Anna Sudha*

Assistant Professor, Sathyabama University.

Sudha, T. A., (2014). Prioritized PWDEDF Scheduling Algorithm For QoS Enhancement Using Network Processor. i-manager’s Journal on Communication Engineering and Systems, 3(1), 1-8. https://doi.org/10.26634/jcs.3.1.2631

Abstract

References

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Identification of the Flood Attackers and effective delivery of Packets in Disruption Tolerant Networks

P. S. Nandhini* , P. Suresh**

* Department of Information Technology, Kongu Engineering College. ** Department of Information Technology, Kongu Engineering College.

Nandhini, P. S., and Suresh, P. (2014). Identification of The Flood Attackers and effective Delivery of Packets in Disruption Tolerant Networks. i-manager’s Journal on Communication Engineering and Systems, 3(1), 9-15. https://doi.org/10.26634/jcs.3.1.2632

Abstract

References

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Analysis and Design of Hysteresis Comparator

M. Bharanidharan* , M. Shenbagapriya**, N. Santhiyakumari***

Bharanidharan, M., Shenbagapriya, M., and Santhiyakumari, N. (2014). Analysis and Design of Hysteresis Comparator. i-manager’s Journal on Communication Engineering and Systems, 3(1), 16-21. https://doi.org/10.26634/jcs.3.1.2633

Abstract

References

Full Article (HTML)

Pdf

Vehicle Speed Violation Control and Tracking using GSM

M. Pratheba* , G. Sekhar**, K. Sivaprakash***

* Assistant Professor, Department of EEE, SNS College of Engineering **-*** PG Scholar, Department of EEE, SNS College of Engineering

Pratheba, M., Sivaprakash, S. K., and Sekhar, G. (2014). Vehicle Speed Violation Control and Tracking Using GSM. i-manager’s Journal on Communication Engineering and Systems, 3(1), 22-27. https://doi.org/10.26634/jcs.3.1.2634

Abstract

References

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Pdf

Design and Implementation of Reconfigurable Microstrip Antenna

M. Alwin* , P. Jothilakshmi**

* M.E Student, Sri Venkateswara college of Engineering, Chennai. ** Assistant Professor, Department of Electronics and Communication Engineering, Sri Venkateswara college of Engineering, Chennai.

Alwin, M., and Jothilakshmi, P. (2014). Design and Implementation of Reconfigurable Microstrip Antenna. i-manager’s Journal on Communication Engineering and Systems, 3(1), 28-32. https://doi.org/10.26634/jcs.3.1.2635

Abstract

References

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Pdf

* Department of Information Technology, Kongu Engineering College.

** Department of Information Technology, Kongu Engineering College.

M. Bharanidharan* , M. Shenbagapriya, N. Santhiyakumari*

M. Pratheba* , G. Sekhar, K. Sivaprakash*

* Assistant Professor, Department of EEE, SNS College of Engineering

-* PG Scholar, Department of EEE, SNS College of Engineering

* M.E Student, Sri Venkateswara college of Engineering, Chennai.

** Assistant Professor, Department of Electronics and Communication Engineering, Sri Venkateswara college of Engineering, Chennai.