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Chirp Scaling Algorithm for Enhanced SAR Data Processing using FPGA

Srinivasulu P.*, Ajay Kumar Dharmireddy**

*-** Department of Electronics and Communication Engineering, Sir C. R. Reddy College of Engineering, Eluru, Andhra Pradesh, India.

Periodicity:January - June'2025
DOI : https://doi.org/10.26634/jcs.14.1.21606

Abstract

Synthetic aperture radar (SAR) imaging is known for its high computational demands, which complicates its use in real- time applications. This paper introduces the chirp-scaling algorithm (CSA) tailored for real-time SAR applications, leveraging advanced field programmable gate array (FPGA) processors. The algorithm employs range Doppler techniques to compress a generated chirp signal, with MATLAB used for validation purposes. To facilitate the computationally demanding tasks like Fast Fourier Transform (FFT) and complex data multiplication, hardware acceleration is essential. Xilinx Vivado is employed to design and implement the required hardware acceleration on the Artix-7 FPGA board. The algorithm's performance has been evaluated through timing analysis and resource utilization. Results indicate reducing 12.4% LUT usage, 52.38% power consumption, significantly enhancing the algorithm's performance, while the speed of multiplication operations has been doubled due to with a modified Booth's algorithm.

Keywords

Signal Processing, Migration Correction, Hardware, Frequency Domain, FPGA, Acceleration.

How to Cite this Article?

Srinivasulu, P., and Dharmireddy, A. K. (2025). Chirp Scaling Algorithm for Enhanced SAR Data Processing using FPGA. i-manager’s Journal on Communication Engineering and Systems, 14(1), 1-12. https://doi.org/10.26634/jcs.14.1.21606

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Chirp Scaling Algorithm for Enhanced SAR Data Processing using FPGA

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