Design of Low Offset Voltage in Second Stage CMOS Operational Amplifier using 90nm Technology

G. Appala Naidu*
Department of Electronics and Communication Engineering, JNTU-GV, College of Engineering Vizianagaram, Andhra Pradesh, India.
Periodicity:January - June'2022
DOI : https://doi.org/10.26634/jcir.10.1.18616

Abstract

In this paper a low offset voltage; low power and high gain second stage op-amp of differential amplifier along with common source amplifier with compensated capacitor is proposed. The mathematical analysis of two-stage op-amp is elaborated and this work is compared with exiting similar work. The experimental work carried in CADENCE Virtuoso with 0 gpdk090 process technology is used to obtain 60.994 of Phase Margin, 61 dB DC gain and Offset voltage is 2mV. The M/L ratios are selected accordingly where supply voltage and load voltage are fixed at 1.8V and 12pF respectively. The parametric analysis helps, where the values are fixed to get better response.

Keywords

Op-amp, Offset Voltage, Phase Margin, Parametric Analysis.

How to Cite this Article?

Naidu, G. A. (2022). Design of Low Offset Voltage in Second Stage CMOS Operational Amplifier using 90nm Technology. i-manager’s Journal on Circuits and Systems, 10(1), 43-48. https://doi.org/10.26634/jcir.10.1.18616

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