Due to declining technologies and increasing design extent, it is becoming high-priced and troublesome to allocate a global clock signal all through the chip. To overcome this, asynchronous processor design is considered as they do not have global clock. In contrary processor industry makes over a change from synchronous to asynchronous logic. Power and robustness differ notably from synchronous to asynchronous circuits. Synchronous blocks which are communicated by asynchronous links in SoC design is a challenging task. Hence, Globally Asynchronous Locally Synchronous (GALS) system is an appropriate technique, as they merge the advantages of both the Synchronous and Asynchronous approaches. International Technology Roadmap for Semiconductors (ITRS) have detailed that the usage of asynchronous logic doubles by 2024. Asynchronous logic resolves the difficulties that occur in synchronization. Fully Synchronous and GALS are two design approaches to detect a signal in the module of the signal processing system. The primary objective is to demonstrate a low power implementation of GALS system.

The system reduces the large Electro Magnetic Interface (EMI) when an active clock is generating large spikes at the supply current in the synchronous circuit. In order to avoid failures of the synchronous circuits, asynchronous wrappers are used for communication in between the synchronous blocks, where the stability of such systems are to be verified. By using asynchronous wrapper in a synchronous island, one can meet the full design requirements and a single die requires large number of clock frequencies because various IP cores are integrated on a complex systems. An efficient technique to design these kind of distributed SoC is GALS. Some clocking schemes are used here to investigate a number of independent clocks on synchronous domains and to obtain reliable transfer of data and low latency. The efficient systems with hardware complexity, global clock rate reduction, and low power consumption use this kind of technique.