Low Power Optimization Technique Based Linear Feedback Shift Register

Dharmendra Singh*, Ankit Singh**, Prachi Agrawal***, Harshita Agrawal****
*-** Assistant Professor, Department of Electronics and Telecommunication Engineering, SSIPMT, Raipur, India.
***-**** UG Scholar, Department of Electronics and Telecommunication Engineering, SSIPMT, Raipur, India.
Periodicity:December - February'2018
DOI : https://doi.org/10.26634/jcir.6.1.14058

Abstract

In Very-Large-Scale Integration (VLSI), the main challenges for the researchers are to reduce the power dissipation by the devices. In this paper, the authors have proposed a modified version of the Linear Feedback Shift Register to meet the specific output. The power consumption can be reduced by deactivating the clock signal from the flip flop to design test pattern generator during testing power. The LFSR pseudo-random test pattern generator is used in the testing of the ASIC chips, which is used to generate the random sequences of the desired pattern generator. This paper will help in the reduction of additional test inputs used for the ASIC. The test pattern is generated in such a way that the component requirements can be reduced.

Keywords

Linear Feedback Shift Register (LFSR), Low Power, Optimization, Built-In Self-Test (BIST), Test Patterns.

How to Cite this Article?

Singh, D., Singh, A., Agrawal, P., and Agrawal, H. (2018). Low Power Optimization Technique Based Linear Feedback Shift Register. i-manager’s Journal on Circuits and Systems, 6(1), 20-24. https://doi.org/10.26634/jcir.6.1.14058

References

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